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Altera_Forum
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15 years ago

Anyone with Experience compiling Stratix IV device w/ over 95% utilization.

Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remainin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Hi,

how many failing paths do you have ? All located in one module or spread over the design ? Do you use design partitions ?

Kind regards

GPK

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Partitions has never worked in the past (always something that keeps full flow from working). In 10.0sp1, it seems to be working. Past problems have been with GXBs and memory IO.

Probably 2k timing violations. Severity is very seed dependant.