--- Quote Start ---
Having trouble getting timing closure with device which is over 95% full (530 GX). The design is also fast and consumes all the memory (figured i should get my money's worth). Of course 5% remaining logic is larger than some of the largest devices 5 years ago. Has anyone else had a large device that is this full?
We are currently focused on Incremental Compile which we have been fighting with 4 years (since 6.0). It looks like it may be actually working in 10.0sp1. Prior to this it was unusable and my team was stuck doing flat compiles.
--- Quote End ---
Hi,
how many failing paths do you have ? All located in one module or spread over the design ? Do you use design partitions ?
Kind regards
GPK
Honored Contributor
