Agilex 3 GTS PCIe IP missing

Hi,

Based on my understanding, mSGDMA (Avalon-MM master) issues memory read/write requests. PCIe Hard IP receives these Avalon-MM transactions. PCIe Hard IP converts them into PCIe TLPs, sends them over the PCIe link. For incoming PCIe TLPs (targeting your FPGA), the PCIe Hard IP converts TLPs into Avalon-MM writes/reads, which mSGDMA can access. In common way, mSGDMA does not build or parse TLPs directly. Instead, it moves data to/from the PCIe Hard IP’s Avalon-MM or Avalon-ST interface. The PCIe Hard IP is responsible for converting Avalon-MM transactions into TLPs (and vice versa). I not sure if your previous implementation sound different or not.

Do I have to handle all TLP myself?? I don't have the experience for this, might not be realistic...

>> detail how the PCIe HIP handle the TLP , you may refer to the user guide under https://www.intel.com/content/www/us/en/docs/programmable/813754/25-1-1/introduction.html

I see online SSGDMA IP DMA PCIe... also only for Agilex 5??

>> At the moment we just enable the ssgdma for Agilex 5,
>> For Agilex 3 we will use MCDMA as instead , the Estimation Delivery Data will be around next year , please stay tune.

There is a PIO design example; even if it works, I also need tx bus mastering.

>> there is build in PCIe PIO example design in Quartus under IP catalog

>> also , PCIe GSRD on https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a3y135b.html

>> For tx bus mastering, we suggest to use MCDMA (to be release in future)

Hope that clarified

Regards,

Wincent_Altera

I need both PIO (simple register access) and DMA (device to host only), the IP for Cyclone V handled this very nicely.

Yes, mSGDMA only handles MM transactions, the rest was done by IP. I mentioned this just for clarity, I expected to find similar functionality for Agilex 3 IP.

I don't think we can afford to wait until next year...

Thanks for your reply,

Gabriel

Hi Wincent,

I don't need SSGDMA explicitly.
I looked through MCDMA IP, and it looks like it offers all I need...

The problem is... the HW is in advanced design stage (I am mostly responsible for firmware) around Agilex 3, it matches the most (we don't need HPS for this project).
Additionally, I see Agilex 3 is already available, but Agilex 5 not.

Otherwise we have a real problem... going back to Cyclone V would be the worst case solution...

If I understand correctly, MCDMA is only "soft" IP. I would be optimistic to get it for A3...

Would it be possible to get some kind of "early beta" access? To be able to progress with my firmware design?

Thanks,

Gabriel

I installed back 25.1 and I was able to create SSGDMA instance.

But I was curious about changes and made a diff between 25.1 and 25.1.1

Among some technical changes, "intel_ssgdma_hw.tcl" (25.1.1) contains:

- set_module_property SUPPORTED_DEVICE_FAMILIES {"Agilex 5" "Agilex 3"}

this sounds nice :), but how about this ???

- # ssGDMA Deprecation Warning
- send_message warning "The sSGDMA IP is not recommended for new projects and is subject to removal in a future release. mSGDMA IP is the recommended replacement for SoC mode. GTS AXI MCDMA IP is the recommended replacement for PCIe mode."

I am confused again...

Regards,
Gabriel

I have the feeling that you miss the whole picture... so let me summarize.

We try to migrate to a new chip generation (Agilex 5/3 with PCIE) and you tell me/us:

- no support in the future for SSGDMA (not "future", even current version 25.1.1 has no support; curiously, the IP got some technical tweaks together with the deprecation note )

- no support for MCDMA for smaller devices (resource tweaks not possible)

- mSGDMA has no PCIE TLP support, not relevant (as the deprecation notes, it's only for SOC/MM)

Forget the "DMA" name, I just need PCIE TLP IP. The old CycloneV IP worked just fine with my design (I used indeed mSGDMA to feed into the tx interface, but I can use my own logic).

What option do I have (or what do you recommend) with PCIE TLP support and smaller devices?? Why are these devices available with PCIE but no IP support?

Regards,
Gabriel

Hi Wincent,

I wrote explicitly... MCDMA (alone!, no user logic) does NOT fit even with minimum settings (PCI 128Bytes, 1 DMA channel).

And you also mention that SGDMA is discontinued...

My only solution right now is to use MCDMA without DMA

That is, just bursting master and slave together with mSGDMA based logic.

This fits into smaller devices... but I have to do low level control to mSGDMA, VFIO... no way to use the MCDMA software/library...

Maybe one day the IP will be improved (to offer reduced memory footprint), but that will probably be too late for me, I need to start the design NOW.

Regards,
Gabriel