Forum Discussion
New ContributorAgilex 3 GTS PCIe IP missing
New ContributorI need both PIO (simple register access) and DMA (device to host only), the IP for Cyclone V handled this very nicely.
Yes, mSGDMA only handles MM transactions, the rest was done by IP. I mentioned this just for clarity, I expected to find similar functionality for Agilex 3 IP.
I don't think we can afford to wait until next year...
Thanks for your reply,
Gabriel
- Wincent_Altera
Regular Contributor
Hi Gabriel,
SSGDMA only available for Agilex 5 , at current viewable roadmap I dont see there is any plan to implement it to Agilex3.
Most similar function based on your requirement will be MCDMA IP.
If you have strong business justification, I will suggest to talk directly to your any Altera Sales Rep/Distributor.
Hoping that this will fasten the development progress.
Let me know if there is anything else I can help
Regards,
Wincent- GabrielC
Hello again,
I tried to play with the MCDMA IP, I just generated the example design.
I used "A5EC065BB32AE4S", a small device which matches most closely to what we planned.
But the compilation fails due to insufficient M20Ks!
(Error(170019): Project requires 489 M20K RAM blocks, but the selected device can contain only 229 M20K RAM blocks)It needs almost 5MBit, almost all memory, but the fitter needs much more blocks.
I don't see any memory requirement settings... do you have any hint?? To tweak the buffers/fifos used inside the IP?
I understand that it could cost the performance, but that's acceptable.
For example, I don't need H2D at all... I would keep it at minimum.
Thanks,
Gabriel
- Wincent_Altera
Hi @GabrielC ,
Based on the error code #170019, I found an information in link below:
In the error message stated that the design memory utilization is too large for the selected device. Hence, you would need to reduce the design. Tips to perform memory optimization
Regards,Wincent
