GabrielC
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Re: Agilex 3 GTS PCIe IP missing
Hi Wincent, I wrote explicitly... MCDMA (alone!, no user logic) does NOT fit even with minimum settings (PCI 128Bytes, 1 DMA channel). And you also mention that SGDMA is discontinued... My only solution right now is to use MCDMA without DMA 🙂 That is, just bursting master and slave together with mSGDMA based logic. This fits into smaller devices... but I have to do low level control to mSGDMA, VFIO... no way to use the MCDMA software/library... Maybe one day the IP will be improved (to offer reduced memory footprint), but that will probably be too late for me, I need to start the design NOW. Regards, GabrielRe: Agilex 3 GTS PCIe IP missing
I have the feeling that you miss the whole picture... so let me summarize. We try to migrate to a new chip generation (Agilex 5/3 with PCIE) and you tell me/us: - no support in the future for SSGDMA (not "future", even current version 25.1.1 has no support; curiously, the IP got some technical tweaks together with the deprecation note 🙂 ) - no support for MCDMA for smaller devices (resource tweaks not possible) - mSGDMA has no PCIE TLP support, not relevant (as the deprecation notes, it's only for SOC/MM) Forget the "DMA" name, I just need PCIE TLP IP. The old CycloneV IP worked just fine with my design (I used indeed mSGDMA to feed into the tx interface, but I can use my own logic). What option do I have (or what do you recommend) with PCIE TLP support and smaller devices?? Why are these devices available with PCIE but no IP support? Regards, GabrielRe: Agilex 3 GTS PCIe IP missing
I installed back 25.1 and I was able to create SSGDMA instance. But I was curious about changes and made a diff between 25.1 and 25.1.1 Among some technical changes, "intel_ssgdma_hw.tcl" (25.1.1) contains: - set_module_property SUPPORTED_DEVICE_FAMILIES {"Agilex 5" "Agilex 3"} this sounds nice :), but how about this ??? - # ssGDMA Deprecation Warning - send_message warning "The sSGDMA IP is not recommended for new projects and is subject to removal in a future release. mSGDMA IP is the recommended replacement for SoC mode. GTS AXI MCDMA IP is the recommended replacement for PCIe mode." I am confused again... Regards, GabrielRe: Agilex 3 GTS PCIe IP missing
Hi Wincent, You missed an important detail again... I wrote explicitly, it fails for Agilex 5 (A5EC065BB32AE4S)!! I chose a similar sized device; the price is also comparable, it could be a good option if it would also be available. But MMap (PIO) and DMA (D2H) is a must, and I need a solution... Regards, GabrielRe: Agilex 3 GTS PCIe IP missing
Hi Wincent, As I wrote here ( community.intel.com/t5/Programmable-Devices/Agilex-3-GTS-PCIe-IP-missing/m-p/1716620#M101270 ), the focus changed to implementing/using on smaller devices (Agilex 5 is similar in price for the similar size, but no availability yet). Should I open a new/dedicated thread? Thanks, GabrielRe: Agilex 3 GTS PCIe IP missing
Hi Wincent, You missed the most important part 🙂 "the example design", I mean ONLY the example design (PCIe x1), no user logic, only generated boilerplate (gts pcie, gts mcdma, system PLL, reset, and 2 small demo onchipmem). The MCDMA IP uses internally a LOT of memory! (e.g. mcdma used memory factor ~70x compared to pcie) It just doesn't fit (memory, not logic) into smaller devices like A5EC065BB32AE4S There are many/big buffers inside the IP (submodules), which need to be adjusted to fit. See the attached report, "dma" is the MCCDMA and "dut" is the AXI PCIE IP. The IP needs tuning parameters. e.g. I don't need H2D and even reordering. Regards, GabrielRe: Agilex 3 GTS PCIe IP missing
Hello again, I tried to play with the MCDMA IP, I just generated the example design. I used "A5EC065BB32AE4S", a small device which matches most closely to what we planned. But the compilation fails due to insufficient M20Ks! (Error(170019): Project requires 489 M20K RAM blocks, but the selected device can contain only 229 M20K RAM blocks) It needs almost 5MBit, almost all memory, but the fitter needs much more blocks. I don't see any memory requirement settings... do you have any hint?? To tweak the buffers/fifos used inside the IP? I understand that it could cost the performance, but that's acceptable. For example, I don't need H2D at all... I would keep it at minimum. Thanks, GabrielRe: Agilex 3 GTS PCIe IP missing
Hi Wincent, I don't need SSGDMA explicitly. I looked through MCDMA IP, and it looks like it offers all I need... The problem is... the HW is in advanced design stage (I am mostly responsible for firmware) around Agilex 3, it matches the most (we don't need HPS for this project). Additionally, I see Agilex 3 is already available, but Agilex 5 not. Otherwise we have a real problem... going back to Cyclone V would be the worst case solution... If I understand correctly, MCDMA is only "soft" IP. I would be optimistic to get it for A3... 🙂 Would it be possible to get some kind of "early beta" access? To be able to progress with my firmware design? Thanks, GabrielRe: Agilex 3 GTS PCIe IP missing
I need both PIO (simple register access) and DMA (device to host only), the IP for Cyclone V handled this very nicely. Yes, mSGDMA only handles MM transactions, the rest was done by IP. I mentioned this just for clarity, I expected to find similar functionality for Agilex 3 IP. I don't think we can afford to wait until next year... Thanks for your reply, Gabriel
