Forum Discussion
New ContributorAgilex 3 GTS PCIe IP missing
Regular ContributorHi @GabrielC ,
Based on the error code #170019, I found an information in link below:
In the error message stated that the design memory utilization is too large for the selected device. Hence, you would need to reduce the design. Tips to perform memory optimization
Regards,
Wincent
New ContributorHi Wincent,
You missed the most important part
"the example design", I mean ONLY the example design (PCIe x1), no user logic, only generated boilerplate (gts pcie, gts mcdma, system PLL, reset, and 2 small demo onchipmem).
The MCDMA IP uses internally a LOT of memory! (e.g. mcdma used memory factor ~70x compared to pcie)
It just doesn't fit (memory, not logic) into smaller devices like A5EC065BB32AE4S
There are many/big buffers inside the IP (submodules), which need to be adjusted to fit.
See the attached report, "dma" is the MCCDMA and "dut" is the AXI PCIE IP.
The IP needs tuning parameters.
e.g. I don't need H2D and even reordering.
Regards,
Gabriel
