New Contributor
Regular ContributorHi Gabriel,
SSGDMA only available for Agilex 5 , at current viewable roadmap I dont see there is any plan to implement it to Agilex3.
Most similar function based on your requirement will be MCDMA IP.
If you have strong business justification, I will suggest to talk directly to your any Altera Sales Rep/Distributor.
Hoping that this will fasten the development progress.
Let me know if there is anything else I can help
Regards,
Wincent
New ContributorHello again,
I tried to play with the MCDMA IP, I just generated the example design.
I used "A5EC065BB32AE4S", a small device which matches most closely to what we planned.
But the compilation fails due to insufficient M20Ks!
(Error(170019): Project requires 489 M20K RAM blocks, but the selected device can contain only 229 M20K RAM blocks)
It needs almost 5MBit, almost all memory, but the fitter needs much more blocks.
I don't see any memory requirement settings... do you have any hint?? To tweak the buffers/fifos used inside the IP?
I understand that it could cost the performance, but that's acceptable.
For example, I don't need H2D at all... I would keep it at minimum.
Thanks,
Gabriel
Regular ContributorHi @GabrielC ,
Based on the error code #170019, I found an information in link below:
In the error message stated that the design memory utilization is too large for the selected device. Hence, you would need to reduce the design. Tips to perform memory optimization
Regards,
Wincent
New ContributorHi Wincent,
You missed the most important part
"the example design", I mean ONLY the example design (PCIe x1), no user logic, only generated boilerplate (gts pcie, gts mcdma, system PLL, reset, and 2 small demo onchipmem).
The MCDMA IP uses internally a LOT of memory! (e.g. mcdma used memory factor ~70x compared to pcie)
It just doesn't fit (memory, not logic) into smaller devices like A5EC065BB32AE4S
There are many/big buffers inside the IP (submodules), which need to be adjusted to fit.
See the attached report, "dma" is the MCCDMA and "dut" is the AXI PCIE IP.
The IP needs tuning parameters.
e.g. I don't need H2D and even reordering.
Regards,
Gabriel
