High Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model

Hi Chee,

thank you for the quick answer.

this is a real problem for me since i am using simulation tool that supports ONLY Verilog.

purchasing this Core i took into account i would be able to use it (and by saying 'using' i mean 'simulate' and 'compile' with the tools i already have).

right now, according to your answer, since there is a mistake and this core documentation is misleading, i need to upgrade the tool i am using for simulation.

i would like to have a solution for this one.

thanks,

Oren

Hi,

i am using ModelSim DE 10.3d

Oren

what is the difference between 'Modelsim* Intel® FPGA Starter Edition' and the 'ModelSim DE 10.3d' i am using? if its free and has the same features i might consider working only with the 'Modelsim* Intel® FPGA Starter Edition'.

i will try and update

hi,

my entire simulation env. is already written so i tried to compile it with the Starter Edition.

i have managed to compile most of it except for the following command which i get an error message:

vlog -sv12compat -timescale 1ns/1ps -l logs/build.log -suppress 2227,2240,2897,2083,139 ../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/tb/top_tb.sv "+incdir+../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/src/stx5" "+define+BFM_LANES=4" "+define+BFM_PIPE=1" "+define+BFM=top_tb.gpipe.bfm" "+define+CHUNK_SIZE=38880" "+define+NUM_OF_CYCLES_AFTER_RESET_BEFORE_START_OF_INJECTION=12" "+define+DATA_BIN_PATH="../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/tb/"" "+define+TEST_NAME=base_fec_adj2" -work work/sim -L xgpon_design -L pcie_hip_com -L reconfig_desi_com

# extra characters after close-quote

do you know why?

thanks,

Oren

hi,

i have tried running the simulation env. using the Starter Edition and i am having many errors (which i dont have when i use the ModelSim DE 10.3d).

i will need your help with this one.

thanks;

Oren