High Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model

Hi Oren, Sorry for the delay. By looking at your previously attached error, sorry as I could not really tell what might be wrong with the compilation. It seems like some type with "extra characters after close-quote" message. As a workaround, I would like to suggest you to start by configuring the IP to your target configuration, then use Generate -> Generate Example Design to generate the example design from the IP. Then try to compile the design using the msim_setup.tcl in Modelsim. Once you are able to compile and get the simulation running. Then you may try to customize from there to your target requirement. Please let me know if there is any concern. Thank you. Best regards, Chee Pin