OLevy1Occasional Contributor7 years agoHigh Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model
CheepinC_alteraRegular Contributor7 years agocan you try using the Modelsim* Intel® FPGA Starter Edition which come with Quartus installation and free.
Recent DiscussionsStratix III FPGA development kitARM DS5 debugger Access/Detection of CM55 on Agilex5 fpga deviceFPGA University Program: Donation Request [UPR-11537]Cyclone VGT Dev Kit boards - some new boards failing to boot from NOR FlashDK-DEV-AGI027RES Install Package