High Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model

Hi Chee,

thank you for the quick answer.

this is a real problem for me since i am using simulation tool that supports ONLY Verilog.

purchasing this Core i took into account i would be able to use it (and by saying 'using' i mean 'simulate' and 'compile' with the tools i already have).

right now, according to your answer, since there is a mistake and this core documentation is misleading, i need to upgrade the tool i am using for simulation.

i would like to have a solution for this one.

thanks,

Oren