OLevy1Occasional Contributor7 years agoHigh Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model
Recent DiscussionsBoard Test System Download Package – Stratix 10 TX Signal Integrity Development KitBoard Test System–Stratix 10TX Development KitBoard TestSolvedAgilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)SolvedDK-DEV-AGI027RBES missing device selection
