High Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model

Hi Oren, As I understand it, you are observing the submodules simulation models are generated in VHDL even though you have selected Verilog. For your information, I have managed to replicate similar observation by using Q17.0. It seems like only top level files are affected by the Verilog or VHDL selection. Based on this observation, I believe there is only one version of submodules models, which is in VHDL available currently. Sorry for the inconvenience. Please let me know if there is any concern. Thank you. Best regards, Chee Pin