High Speed Intel Reed Solomon Simulation Model Submodules are being generated in VHDL although i select Verilog Simulation Model

hi,

my entire simulation env. is already written so i tried to compile it with the Starter Edition.

i have managed to compile most of it except for the following command which i get an error message:

vlog -sv12compat -timescale 1ns/1ps -l logs/build.log -suppress 2227,2240,2897,2083,139 ../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/tb/top_tb.sv "+incdir+../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/src/stx5" "+define+BFM_LANES=4" "+define+BFM_PIPE=1" "+define+BFM=top_tb.gpipe.bfm" "+define+CHUNK_SIZE=38880" "+define+NUM_OF_CYCLES_AFTER_RESET_BEFORE_START_OF_INJECTION=12" "+define+DATA_BIN_PATH="../../FPGA/4x10/MAC/Branches/v5042_oren_dbg/tb/"" "+define+TEST_NAME=base_fec_adj2" -work work/sim -L xgpon_design -L pcie_hip_com -L reconfig_desi_com

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do you know why?

thanks,

Oren