fail to compile after assigned the SFP_TX_P1 of SFP+ module (arria V gx dev kit)

correction: the pin number is PIN_W37, not PIN_W36

That's almost the same issue that I have at the moment. Actually in the pin assignment at the reference manual it says that the SFP pins have the 3.3V/LVTTL I/O Standard but I cannot choose it in Quartus. Any ideas?

I'm curious if any of you solved this. I'm getting the same type of error that isn't giving me a lot to go on. This is related to some LVDS RX inputs I'm using with altlvds_RX on the Cyclone V (Bemicro CV eval board).

Hi!

Thanks Eduardo, I think in my case the problem was solved by keeping all the pins constrained to one region. I had to move the LVDS to another connector. I had originally assumed that all of the LVDS RX pins brought to the headers were from the same bank but that was not the case. I wish the error would have been more clear, but I am past it at this point.

Oh yes, now I remember that I had problems with the location of the clock pin that I was using for the transceiver clock. It had to be one that was in the same bank or at least a special location close to the SFP module.

HI