Forum Discussion
Honored Contributorfail to compile after assigned the SFP_TX_P1 of SFP+ module (arria V gx dev kit)
I want to use the SFP+ module which converts electric signal to optical signal to transmit some data.
I use the arria V gx dev kit. I assigned the data to pin PIN_W37 and select the i/o standard as "1.5-V PCML" in "pin planner". It automatically generates an output names "SFP_TX_P1(n)" as an differential pair. When compiling it keeps saying "Error (175020): Illegal constraint of pin to the region (0, 47) to (0, 47): no valid locations in region Info (175028): The pin name: SFP_TX_P1 Error (184016): There were not enough differential output pin locations available (1 location affected) Info (175029): pin containing PIN_W37 Info (175015): The I/O pad is constrained to the location PIN_W37 due to: User Location Constraints (PIN_W37)" could someone help to tell me what is the problem. appreciate~9 Replies
Altera_Forumcorrection: the pin number is PIN_W37, not PIN_W36
- Altera_Forum
That's almost the same issue that I have at the moment. Actually in the pin assignment at the reference manual it says that the SFP pins have the 3.3V/LVTTL I/O Standard but I cannot choose it in Quartus. Any ideas?
- Altera_Forum
I'm curious if any of you solved this. I'm getting the same type of error that isn't giving me a lot to go on. This is related to some LVDS RX inputs I'm using with altlvds_RX on the Cyclone V (Bemicro CV eval board).
It seems like it is failing some "legality" check, but it isn't providing a lot of insight into what I can do about it. Searches haven't provided a lot of information. Thanks, Lance - Altera_Forum
Hi!
I don't remember exactly how I worked around this right now. If I remember correctly, that error can also be caused by a bad configuration of the transceiver block. I used the 1.5 V PCML I/O Standard for the serdes input and output pins and 2.5V for the rest. I also set the transmitter disable to 0 to activate the transmitter. Regards Eduardo - Altera_Forum
Thanks Eduardo, I think in my case the problem was solved by keeping all the pins constrained to one region. I had to move the LVDS to another connector. I had originally assumed that all of the LVDS RX pins brought to the headers were from the same bank but that was not the case. I wish the error would have been more clear, but I am past it at this point.
Regards, Lance - Altera_Forum
Oh yes, now I remember that I had problems with the location of the clock pin that I was using for the transceiver clock. It had to be one that was in the same bank or at least a special location close to the SFP module.
Regards - Altera_Forum
HI
I was facing with the same issue. i have assigned clk,tx and rx differential pins in the same IO bank in pin planner and IO standard is 1.5V PCML while compiling its giving error as Error (175020): Illegal constraint of pin to the region (183, 42) to (183, 42): no valid locations in region Info (175028): The pin name: FO_RX_P[1] Error (184016): There were not enough differential input pin locations available (1 location affected) Info (175029): pin containing PIN_T1 Info (175015): The I/O pad is constrained to the location PIN_T1 due to: User Location Constraints (PIN_T1) Please help me out - Altera_Forum--- Quote Start --- HI I was facing with the same issue. i have assigned clk,tx and rx differential pins in the same IO bank in pin planner and IO standard is 1.5V PCML while compiling its giving error as Error (175020): Illegal constraint of pin to the region (183, 42) to (183, 42): no valid locations in region Info (175028): The pin name: FO_RX_P[1] Error (184016): There were not enough differential input pin locations available (1 location affected) Info (175029): pin containing PIN_T1 Info (175015): The I/O pad is constrained to the location PIN_T1 due to: User Location Constraints (PIN_T1) Please help me out --- Quote End --- Are you using general purpose IOs or transceiver IOs? 1.5V PCML is only for transceiver IOs.
- Altera_Forum--- Quote Start --- Are you using general purpose IOs or transceiver IOs? 1.5V PCML is only for transceiver IOs. --- Quote End --- Yes..I am using transceiver IOs.
