Agilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)
Device: A5ED013BB32AE4SCS Quartus Prime Pro 25.1.1 Build 125 I am trying to reconfigure a standalone fabric IOPLL at runtime using the EMIF Calibration IP (emif_io96b_cal), following the HSIO reconfiguration flow described in the Clocking and PLL User Guide (813671), section 6.1/6.4, and the approach discussed in this thread: Agilex 5 reconfigurable PLL - emif | Altera Community - 122952 Setup: - ps_pll: Intel IOPLL FPGA IP, "Enable dynamic reconfiguration of PLL using Calibration IP" = true, IOPLL Type = "I/O Bank" (only selectable value in the GUI), 50 MHz reference clock. - EMIF Calibration IP (emif_io96b_cal), INSTANCE_ID = 0, NUM_CALBUS_PLLS = 1, NUM_CALBUS_PERIPHS = 0, AXI4-Lite subordinate port in FABRIC mode. - pll_calbus / pll_calbus_readdata wired directly between the two IPs. The Fitter fails during the very first placement/plan stage with: Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Error(175001): The Fitter cannot place 1 IOPLL, which is within IOPLL FPGA IP ps_pll_altera_iopll_2000_ihvozry. Error(16234): No legal location could be found out of 11 considered location(s). Error(175005): Could not find a location with: HVIO_IOPLL (6 locations affected) Error(175008): Location was not in the legal region (5 locations affected) I isolated this down to a minimal reproduction: 1) A plain, non-reconfigurable IOPLL alone: places fine. 2) The same IOPLL with calbus reconfiguration enabled, standalone (no EMIF IP at all): places fine. 3) The EMIF Calibration IP alone, calbus tied off, unconnected to any PLL: places fine. 4) The reconfigurable IOPLL and EMIF Calibration IP both present in the same design but NOT wired together (calbus tied off independently on each side): places fine. 5) The reconfigurable IOPLL wired to the EMIF Calibration IP via calbus (the actual intended configuration): fails with the error above, 100% reproducible, regardless of I/O pin location assignments (confirmed by removing every pin constraint from the design entirely - identical error, identical 6+5 location breakdown). I have also tried, with no change to the error: - Removing all pin location assignments (refclk, PLL outputs, etc.) - Setting PLL_REFCLK_INPUT_TYPE to NOT_BALANCED on the IOPLL instance - Quartus Interface Planner tool - "Update Plan" fails immediately with the identical underlying Fitter conflict, before it can even display a plan. Can someone from Intel/Altera help me understand what is actually driving this placement conflict and how to resolve it? Happy to share the minimal reproduction project if useful.Intermittent DE10-Standard error starting GDB server with quartus_hps
Hello, We have 15 DE10-Standard boards being used with Quartus 18.1 and the associated version of Altera Monitor Program on Ubuntu 24.04 (amd64). Generally the boards work without issue, however in the Monitor Program we occasionally see 'Download System - Partial Success: The system has successfully downloaded onto the board, but HPS components could not be configured.' Power cycling the board doesn't seem to resolve the error, nor does swapping the board to a different desktop. After a number of tries the error will go away. We haven't been able to isolate an exact pattern but issue doesn't appear random either, it will keep showing up for certain boards, and then go away, then show up on other boards. Another symptom we see is that when a board downloads the systems successfully, during the final step of the process the JTAG TX LED on the board appears to turn solid green. On the boards that hang and fail, the same LED flashes rapidly while the process hangs. The monitor program logs show the following commands are run before the error appears: $ /home/$USER/DE10/monitorprogramtutorial/ $ make clean # The board name in quotes below is variable and appears to be unique to each board or connection $ /opt/intelFPGA_lite/18.1/quartus/bin64/quartus_pgm -c "DE-SoC [1-10]" --auto $ quartus_pgm -c "DE-SoC [1-10]" -m jtag -o "P;/opt/intelFPGA_lite/18.1/University_Program/Computer_Systems/DE10-Standard/DE10-Standard_Computer/verilog/DE10_Standard_Computer.sof@2" $ quartus_hps --cable="DE-SoC [1-10]" -o GDBSERVER --gdbport0=3212 --preloader=/opt/intelFPGA_lite/18.1/University_Program/Monitor_Program/arm_tools/u-boot-spl.de10-standard.srec --preloaderaddr=0xffff14f0 Running these commands manually results in the final command either: 1. Starting a GDB server very quickly: >>Resetting HPS. >>Downloading preloader....... >>Program loaded. PC set to program entry (0xFFFF0000) >>Setting vector base address register to: 0xffff0000 >>Running preloader.. >>Preloader successfully run. Starting GDB Server. Listening on port 3212 for connection from GDB 2. Hanging for a long time when 'Downloading preloader.......' and then failing at the 'Running preloader...................' stage and hanging indefinitely. Ending the process with Ctrl+C shows: Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: Fail to enable DEBUG feature Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 1 Error: Fail to READ ACCESS to the Physical Reg Error: Failed to load program. Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Encounter JTAG AJI error while reading Control/Status Register Error: AJI failed to send data Error: Encounter JTAG AJI error while accessing HPS Error: send_access_data() error while accessing DP Register Error: Fail to select Access Port Error: Fail to access Bank 0x0 of Port 0 Error: Fail to READ ACCESS to the Physical Reg Error: Fail to write to MPU Module Reset Register Error: Engine failed to set down the hardware Error: Quartus Prime Programmer was unsuccessful. 0 errors, 0 warnings Error: Peak virtual memory: 187 megabytes Error: Processing ended: Tue Aug 11 11:44:38 2026 Error: Elapsed time: 00:05:05 Error: Total CPU time (on all processors): 00:00:01 Any thoughts or suggestions are greatly appreciated.
AXI4-Lite Firewall IP core - Altera support request
Greetings Altera, Just FYI, I writing in the community forum, in addition to a sent an inquiry yesterday, through the website contacts form - https://www.altera.com/contact - in attempt to get into contact and start a conversation going with some of your FAEs regarding a problem our company and team is facing: Currently in one of our FPGA Designs utilizing Altera FPGAs (CycloneV SoC ARM (5CSEBA5)), there is a requirement to monitor and control data streams/transfers between AXI4 master and slave devices. We have to ensure those are occurring in the allowed (configurable) address ranges, and if not, such data transfer is canceled – both downstream and upstream, the master is kept aware, and an interrupt is driven out. A Nios II CPU shall be able to configure (access) this IP core – set these address ranges, read statuses, etc. Also it will be the recipient of the IRQ from core in case of faults. Basically, we are looking for a simple configurable (read&write) AXI4-Lite Firewall/Pass-through/Configurable Bridge (whatever you want to call it) type of IP core – that will sit between two AXI connected type devices (master on one-side & slave on the other) and oversee the communication between them. For Altera Cyclone V SoC FPGAs. At this point we cannot find such component from the Altera’s Quartus IP cores (Platform Designer) library. Also, it is not obvious for us how to, or, even if it is possible to ‘construct’ such device, from other IPs already available in the library ??? That’s why I am reaching to you for support on the matter. To check what approach or solution can you suggest , do you have anything available as service or ip core that could solve our problem, recommend us an IP vendor , etc... Here's a general block diagram of what we have in mind: (download the attached .png for better resolution) I hope we can talk soon. Best Regards, - Georgi M.
SOLVED: BSP Editor NullPointerException on Debian 13 Linux
SOLVED: BSP Editor "New BSP" menu command is grayed out, so can't make any new BSP's, and opening any existing one from another computer throws: SEVERE: Available BSP type values for the --type argument are: [] SEVERE: BSP type "hal2" unknown. SEVERE: NullPointerException Based on other forum posts with a similar error, it seems like this is because the BSP Editor couldn't locate some of its own files. That seems likely here too since this is the first time it's used on this computer. But there's no problematic install path etc since I used the default. THERE ARE NO SPACES IN THE INSTALL PATH NOR THE PROJECT PATH. Everything else is working already for the Max 10: I can generate with Platform Designer, synthesize with Quartus, program SRAM with SignalTap, debug Nios V with RiscFree. Details are: Quartus Prime Lite 25.1std.0 Build 1129 10/21/2025 SC Lite Patches: None OS: Debian 13. This is what Ubuntu is based on, so it's very similar. And like I said everything else already works. USB came online already, not too hard. All it took was the Altera udev rules file 92 as usual, and the correct LD_LIBRARY_PATH so jtagd could find its own shared libs. Installed quartus into regular user account, not whole system, not as root. This is offered as an option in the installer if I recall correctly. Install path is the installer's default: /home/myuser/altera_lite/25.1std The project files are irrelevant here, since BSP Editor is already off-track as soon as it launches. "New BSP" is grayed out. SOLVED: BSP Editor is unable to find its own files without Altera's environment vars, which are provided when running inside niosv-shell. That's nonsensical to me, since any brain-dead program off the street can detect where its own binary loaded from, on any OS, and walk up the path from there to find the rest of its files, as a default if no env vars were provided. That's the first line of every binary or Tcl script I've ever written. Quartus main GUI seems to do it exactly that way. Anyone else struggling with this inexplicable rough edge should make sure your desktop's launcher icon invokes niosv-shell first, like this: altera_lite/25.1std/niosv/bin/niosv-shell --run altera_lite/25.1std/niosv/bin/niosv-bsp-editor To Altera: if you're struggling to maintain or improve your software because it relies on Tcl, contact me through my forum account. I could clean up a whole mess of rough edges like this one, and some other much-needed improvements.
Starting Quartus GUI fails in docker version
Hi, Recently I found out Quartus is available for docker. I started to test and compile process worked well on an existing design with 25.1 Standard Edition on both native SUSE Linux and WSL (SUSE as well). But when I wanted to start the GUI, I got back the following error (in both cases): /mnt/c/Windows/system32> docker run --net=host alterafpga/quartus-std:25.1std-all quartus *** Fatal Error: Segment Violation at (nil) Module: quartus Stack Trace: 0x289a2: abort + 0x182 (c.so.6) 0xae55a: QtPrivate::lcNativeInterface() [clone .cold] (Qt6Core.so.6) 0xaedc4: QMessageLogger::warning(char const*, ...) const (Qt6Core.so.6) 0xf9dc2: QGuiApplication::restoreOverrideCursor() [clone .cold] (Qt6Gui.so.6) 0x18e5a1: QGuiApplicationPrivate::createPlatformIntegration() + 0x641 (Qt6Gui.so.6) 0x18ef00: QGuiApplicationPrivate::createEventDispatcher() + 0x30 (Qt6Gui.so.6) 0x1461f5: QCoreApplicationPrivate::init() + 0xbe5 (Qt6Core.so.6) 0x1921b3: QGuiApplicationPrivate::init() + 0x33 (Qt6Gui.so.6) 0x18bc59: QApplicationPrivate::init() + 0x9 (Qt6Widgets.so.6) 0xb3899: AFCQ_APP::AFCQ_APP(int&, char**) + 0x13 (gcl_afcq) 0x6863a: QUI_APP::QUI_APP(int&, char**) + 0x1e (sys_qui) 0x14fb9: QGQ_APP::QGQ_APP(int&, char**) + 0x9 (sys_qgq) 0x38b8: qgq_main(int, char const**) + 0x48 (quartus) 0x3e540: msg_main_thread(void*) + 0x10 (ccl_msg) 0x5c1c: thr_final_wrapper + 0xc (ccl_thr) 0x3e60a: msg_thread_wrapper(void* (*)(void*), void*) + 0x6e (ccl_msg) 0xc046: mem_thread_wrapper(void* (*)(void*), void*) + 0x96 (ccl_mem) 0x9188: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err) 0x5c5f: thr_thread_wrapper + 0x15 (ccl_thr) 0x4050a: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa8 (ccl_msg) 0x39d5: main + 0x26 (quartus) 0x2a28b: __libc_start_main + 0x8b (c.so.6) 0x37aa: _start + 0x2a (quartus) End-trace Is this a compatibility issue with my Linux version? Or do I make something wrong? Best regards, IstvanQuesta-ModelSim UI scaling problems in Linux
Hello Has anybody been able to solve the issue of UI of Questa not scaling correctly on linux with wayland? I am using Ubuntu 26.04 with wayland and UI is just tiny, icons, are so small i cannot read any text. When opening a new project, file explorer is also tiny. Fonts i could change in the config file but icons, menus and everything else is just extremely small. Problem is even worse on high resolution displays. Regards, Haris
Quartus Licensing Issue
Recent versions of Quartus (both Std & Pro) for WIndows introduced a new problem with the license management (for node-locked licenses) which is a pain to work around. In Tools > License Setup panel, "NIC ID", a lot of "ghost" adapters appear now, while the normal behavior was to see the MAC Addresses of the Ethernet Adapters that show up in the device manager and in ipconfig /all. This seems aggravated by the use of the "Get no-cost licenses" button that apparently generates a license file for a (or many !) new virtual adapter(s)... I call them "ghost" or virtual because they don't show up in the usual commands (getmac /v, ipconfig /all, lmhostid etc) and do not correspond to a physical peripheral (network card). To make things worse, Quartus can apparently only handle a maximum of 10 (ten) Ids. The consequence is that your "real" adapter may fall out of the list and a node-locked license for this adapter becomes unusable. The only work around I found was to use the device manager, display the hidden devices, and to disable the numerous Microsoft "WAN Miniport" in the Network cards category. This should reduce the list enough to see the "real" address used for your node-locked license. I proposed a solution : allow the manual editing of the NIC Ids list (save in quartus.ini or registry). But today it seems a bit hard to be heard...
