However, after programming an SD Card with this image, as far as I can tell, my board doesn't boot. I get no output from the serial port so I don't have any way of debugging.
Please can you help with any advice how to proceed to diagnose what is going wrong?
I am in charge of updating the build instructions related to Agilex 5 and we want to improve these as much as we can. Could you please provide more details of the configuration that you needed to do to boot successfully?
You mentioned that you needed to change socfpga_cyclone5_defconfig, may I know why you started with this defconfing instead of the one specific for Agilex 5 ( socfpga_agilex5_defconfig )?
for the Boot from QSPI but have given up as, having got around a number of errors, I managed to create and program my QSPI, only for to fail to boot (I can't even open the Serial Port), at which point I have no way to debug what is happening...
One error that I have relates to bl31.bin which i built successfully in the Boot from SD Card stage, but when I run bitbake in the QSPI stage, i get this error:
DEBUG: Executing shell function do_compile cp: cannot stat '/home/malc/agilex5_top/yocto/build/tmp/deploy/images/agilex5_dk_a5e065bb32aes1/bl31.bin': No such file or directory WARNING: /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/temp/run.do_compile.19724:163 exit 1 from 'cp /home/malc/agilex5_top/yocto/build/tmp/deploy/images/agilex5_dk_a5e065bb32aes1/${file} /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/build/${config}/${file}' WARNING: Backtrace (BB generated script): #1: do_compile, /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/temp/run.do_compile.19724, line 163 #2: main, /home/malc/agilex5_top/yocto/build/tmp/work/agilex5_dk_a5e065bb32aes1-poky-linux/u-boot-socfpga/v2025.04+git/temp/run.do_compile.19724, line 301
PS. I am using WSL2.
In the boot from QSPI section, it is unclear what, if anything I need to do with the SD Card...
This section presents how to boot from QSPI. One notable aspect is that you need to wipe the SD card partitioning information, as otherwise U-Boot SPL could find a valid SD card image, and try to boot from that first.
Wipe SD Card
Either write 1MB of zeroes at the beginning of the SD card, or remove the SD card from the HPS Daughter Card. You can useddon Linux, orWin32DiskImageron Windows to achieve this.
Write QSPI Flash
1. Power down board
2. Set MSEL dipswitch S4 on SOM to JTAG: OFF-OFF
3. Power up the board
4. Download and extract the JIC image, then write it to QSPI:
Related to the errors that you are seeing when building the binaries, it's possible that a package could be missing in the WSL2 environment when building the RootFS, but what is weird is that in this page https://altera-fpga.github.io/rel-25.1.1/embedded-designs/agilex-5/e-series/modular/boot-examples/ug-linux-boot-agx5e-modular, you just use the rootfs in the Linux boot stage and shouldn't affect that you see something on the serial console. The U-Boot SPL is the first binary that HPS executes and this is included as part of the bitstream provided to the system. This bitstream includes the hardware design(.sof) and the SPL(.hex):
In the case of booting from SD Card:
In the case of Booting from QSPI:
If the hardware design(.sof) and the SPL(.hex) were created correctly, you should be able to see an output from the serial console. here you also need to double-check that in your devkit, the msel is set to QSPI so it can read the bitstream from the QSPI.
If you have problems generating the RootFS, you can get this directly from the Pre-Built binaries included in the correct paths provided above.
So unless Altera drop any support on C5,A5 I cannot see the default config can work proper on the 2025 same as previous 2024 or even older version of spl configurations.
I don't think we had drop the support of these devices, but the embedded software (including U-Boot) evolves from release to release. Sometimes, there are dependencies on using the correct component versions to boot successfully ( SDM FW included on Quartus, ATF. U-Boot SPL, U-Boot, Linux). So in our releases pages (https://github.com/altera-fpga/gsrd-socfpga/releases) we include the combinations of components that we validate. For GSRD page or any other page with instructions to build binaries, we have a version of the page for each one of the releases with the component version combinations that we know they work. For this pages, we switched from Rocketboards to https://altera-fpga.github.io/ some time ago. For Agilex 5, I think most of the versions are already in the new site.
I am not pointing on the stage after SPL aka U-Boot. Only focusing on SPL aka the HPS ARM ROM detecting the SPL etc.
I cannot see this is related to component variant. b.c. as long as the HEX data on the MBR sanity is good. Then it should at least provide message on serial port.
However on 2025 01 or 04 it is not able to do so on default cyclone_V defconfig file passed along version of U-Boot.
Our documentation and HPS releases are based on the Altera repositories (https://github.com/altera-fpga). Please look at our Release Notes page that shows what versions of each component we released:
In the case of U-Boot, the latest release is based on 2025.04. The next release will be based in 2025.07.
We are working to push all the updates that we have in our repositories to the repositories that the community supports (i.e. https://github.com/u-boot/u-boot) but it's possible that the latest code in the Altera repos are not yet propagated to the community repos, so this is the reason why we direct our customers to use the Altera repos.
If you have any further questions about Cyclone V, it would be better to open a new case, so we can focus in this case to solve the issues related to Agilex 5.
Is is not recommended to always grab the latest uboot branch, the latest branch has the latest updates and patch that was pushed for any on going issues.
Please refer to the last verified combination in the Altera GitHub page.
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