SD Card Boot
Hi, I have an Agilex 5 Modular Development Board which I can boot with the supplied SD Card. I have tried to update to the latest image at Index of /2025.04/gsrd/agilex5_mk_a5e065bb32aes1_gsrd/, However, after programming an SD Card with this image, as far as I can tell, my board doesn't boot. I get no output from the serial port so I don't have any way of debugging. Please can you help with any advice how to proceed to diagnose what is going wrong? Many thanks Malcolm
How to customize the Agilex 7 I-series OS build with SOF and HPS changes ?
Hi Team, So we are working with Agilex 7 I-series Evaluation kit, We have successfully built yocto image for the GSRD as explained in this guide : https://altera-fpga.github.io/rel-24.3.1/embedded-designs/agilex-7/i-series/soc/gsrd/ug-gsrd-agx7i-soc/#set-up-yocto And the board boots up fine, and tested the led example applications as well. Now we want to add our own SOF exported from Quartus Prime Pro design and re-build the OS. NOTE: The Quartus design may contain some interrupts, msgDMA, and GPIO's. I have a few questions: Apart from the SOF file, what other file needs be generated from Quartus Prime ? Where is the dts, which we can customize for HPS & FPGA-HPS ? What's the build flow for such a customized design. Since the guide only explains about the GSRD, Can you explain the flow for custom designs ? Regards, Sujan
Agilex5 .sof programming error
Has anybody ever seen this error when trying to program a design with a .sof: CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A55/A76) Model: SoCFPGA Agilex5 Terasic Atum A5 DRAM: 2 GiB (effective 4 GiB) Core: 47 devices, 25 uclasses, devicetree: separate WDT: Not starting watchdog@10d00200 WDT: Not starting watchdog@10d00300 WDT: Not starting watchdog@10d00400 WDT: Not starting watchdog@10d00500 WDT: Not starting watchdog@10d00600 NAND: 0 MiB MMC: mmc0@10808000: 0 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1... Loading Environment from UBI... "Synchronous Abort" handler, esr 0x96000010, far 0x108d2000 elr: 0000000080263ce8 lr : 0000000080263ef4 (reloc) elr: 00000000ffd54ce8 lr : 00000000ffd54ef4 x0 : 00000000108d2000 x1 : 0000000000003228 x2 : 00000000ff8f4d30 x3 : 0000000000003260 x4 : 0000000000004e3c x5 : 0000000000006320 x6 : 0000000000003234 x7 : 0000000000000001 x8 : 00000000ff8e8a70 x9 : 0000000000003228 x10: 00000000ff8e65ec x11: 0000000000000798 x12: 0000000000000000 x13: 00000000ff8e8a70 x14: 00000000ffffffff x15: 00000000ff8e643d x16: 00000000ffcfdb90 x17: 0000000000000000 x18: 00000000ff8eed90 x19: 00000000ff8f4d30 x20: 00000000ff8f1360 x21: 00000000ff8f12c0 x22: 00000000ff8fb3b0 x23: 0000000000000001 x24: 0000000000000000 x25: 0000000000000000 x26: 0000000000000000 x27: 0000000000000000 x28: 0000000000000000 x29: 00000000ff8e6750 Code: 32000021 d5033fbf b9000001 d65f03c0 (b9400001) Resetting CPU ... ### ERROR ### Please RESET the board ### I am using this build flow for the OS, and the GHRD from CDROM v1.4.0 It is worth noting that when programming with the .jic generated by the same project using: quartus_pfg -c golden_top_hps.sof golden_top_hps.jic -o device=MT25QU512 -o flash_loader=A5ED065BB32AR0 -o mode=ASX4 There is no such issue. Thanks
cross compiler for cyclone 5
hii i have a kernel module that prints hello world in the kernel space , i tried to use cross complier = arm-linux-gnueabihf-gcc and it didn't work for me i get invalid format when i run the file on my cyclone 5 de1 board i remember that someone suggest for me to use complier that has the word none in it could you please give me the full name of the cross compiler with the none in it ?
Reconfigure FPGA Agilex 7 M-series without recompile Yocto Linux
Hi, We have Agilex 7 M-series. We managed to run an example of Yocto Linux on the ARM core, and based on my understanding, every time we have a new bitstream, we need to compile Yocto again and rewrite the SD card. right? So, I guess there is no Ubuntu support or ready for ARM core in Agilex 7, like in Xilinx Zynq, they have Ubuntu support. But in our FPGA, we want to find a way to reconfigure the FPGA fabric without re-burning the SD card. Is it in any way possible to do that? I noticed about configure via AVSTx8. But I am still confused about that and still doubt if that's what I need or not, because it says after reboot, it will be stuck, so there is no reboot for the ARM core. Please help me with a hint or info regarding that. Thank you very much. Best regards, IhsanHPS to FPGA bridge in GSRD Agilex 7 m-series
Hi, I am following this tutorial to generate the GSRD for my fpga https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/ everything work, until I want to test the HPS to FPGA bridge. At least, the LW bridge has been used in the design for controlling the LEDs, right? but I cannot manage to find out how to access or manipulate it? Does the bridge include in the GSRD? or no? Thank you.Linux kernel source for SoC FPGA Intel
Hi, I notice that there are two sources for building a Linux kernel for SoC FPGA. First is https://github.com/altera-fpga/linux-socfpga, and the second is https://github.com/altera-fpga/gsrd-socfpga . Could anyone give an easy explanation about the differences? And when should I use one of those? Thank you.Agilex 7 M-series GSRD wrong DDR5 memory size
Hi, I followed the development of GSRD for Agilex 7 M-series, like in https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/ When I boot, I get init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success io96b_mb_init: num_instance 1 io96b_mb_init: get memory interface IO96B 0 io96b_mb_init: IO96B 0 mem_interface 0: ip_type_ret: 0x1 io96b_mb_init: IO96B 0 mem_interface 0: instance_id_ret: 0x0 io96b_mb_init: IO96B 0: num_mem_interface: 0x1 DDR: Warning: DRAM size from device tree (2048 MiB) mismatch with hardware (4096 MiB). DDR5: 2048 MiB ecc_enable_status: ECC enable status: 0 DDR5: size check success DDR5: firewall init success DDR5 init success So I am thinking of changing the size of DRAM in the device tree, but I cannot find out where I should change it. Could anyone help me find out? Thank you.Agilex 5 LPDDR4 8GB
Hi, What's the lowest density Agilex 5 supports 8GB of LPDDR4? I'd appreciate if someone can point me to the correct documentation that shows which device density supports 8GB. Our project requires at least 2 HPS (quad preferred) and 8GB of memory. The project will use Linux OS and has minimal FPGA logic requirement and also don't require any transceivers. Thanks, Jol