SueC_Altera
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Re: Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA
Hi Dr. Barry H, I put the link in my text, but it didn't work! :-( It also won't let me just paste the link. I don't know why! Paste this link in your brower: https://www.intel.com/content/www/us/en/design-example/843487/agilex-7-nios-v-m-processor-with-ddr-dma-and-ocm-design-example.html Sue35Views1like6CommentsRe: Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA
Hi Dr Barry H, I don't see that exact example. There's a Nios V on Max 10 example here. There's a Nios V with mSGDMA on Agilex 5 here. I wonder if you can use those to figure out what you need to know. Please let me know. Thanks, Sue33Views1like1Comment- 31Views0likes0Comments