SueC_Altera
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Re: U-Boot "Synchronous Abort" boot failure on Terasic Atum A5 Rev B via Quartus 24.3 .jic generation
Hi Motaz_sami, Thanks for posting your solution. That is super helpful to the community. Please review these examples: https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/documentation/01_index.md There are a couple in there that enable the bridges. Sue38Views0likes1CommentRe: Where is FreeRTOS-Plus-TCP Design
Hi JLee25, The best starting place would probably be the Arria 10 TSE design. https://docs.altera.com/r/docs/8d454826ee7e62a6a8cdc48813f402492c721691adbd373753ddc9ccedd00290-introduction/arria-10-fpga-triple-speed-ethernet-with-ieee-1588v2-and-native-phy-design-example/introduction Sue40Views0likes0CommentsRe: Agilex 5E ES Memory Performance Issues
Hello PHe, You are correct that the performance degradation in the ES devices is due to the errartum you mentioned. This erratum has been addressed in the production devices and the performance is greatly improved. We have included a benchmark example in the 26.1 Golden System Reference Design (HPS Baseline Example Design) that you can use to run standard benchmarks to see the performance. Regards, Sue100Views2likes0CommentsRe: Nios V license
Hi BXia, You have to also register for the Self Service Licensing Center (SSLC) before you can sign in. Please go there and click on the register link. For some reason, I can't put the link in this reply, but if you google Altera SSLC it will take you there. Please let me know if that works. Thanks, Sue29Views0likes0Comments