KennyT_altera
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Re: About Dual Simplex for Agilex 3
Altera have not officially announced a specific future Quartus Prime version that will support Dual Simplex (DS) mode for Agilex 3 FPGAs. The documentation and Altera support forums do not list a planned release or timeline for this feature. Altera's Guidance The user guide you referenced is regularly updated, and any changes in device or feature support (including DS mode for Agilex 3) will be documented in future releases. For the most accurate information, Altera recommends, monitoring the Release Notes for Quartus Prime.17Views0likes0CommentsQuartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.137Views0likes16Comments