Wrong logic synthesis when call function named <package_name>.<function_name>

I am in trouble in VHDL analyze & synthesis.

library ieee;
use     ieee.std_logic_1164.all;
package Sample is
    subtype   Code_Type  is std_logic_vector(3 downto 0);
    function  New_Code_0 return Code_Type;
    function  New_Code_1 return Code_Type;
    function  New_Code_2 return Code_Type;
    function  New_Code_3 return Code_Type;
end Sample;
package body Sample is
    function  New_Code_0 return Code_Type is begin
        return std_logic_vector'("0001");
    end function;
    function  New_Code_1 return Code_Type is begin
        return std_logic_vector'("0010");
    end function;
    function  New_Code_2 return Code_Type is begin
        return std_logic_vector'("0100");
    end function;
    function  New_Code_3 return Code_Type is begin
        return std_logic_vector'("1000");
    end function;
end Sample;

library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;
use     work.Sample;
entity  Sample_NG is
    port (CLK: in  std_logic;
          CLR: in  std_logic;
          O  : out Sample.Code_Type
    );
end     Sample_NG;
architecture RTL of Sample_NG is
    signal count : integer range 0 to 3 := 0;
begin
    process(CLK) begin
        if (CLK'event and CLK = '1') then
            if (CLR = '1' or count >= 3) then
                count <= 0;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
    O <= Sample.New_Code_3 when (count = 3) else
         Sample.New_Code_2 when (count = 2) else
         Sample.New_Code_1 when (count = 1) else
         Sample.New_Code_0;
end RTL;

Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 15.1.0 Build 185 10/21/2015 SJ Lite Edition
    Info: Processing started: Tue Mar 15 00:50:13 2016
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 0020 -c sample_ng
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file sample_ng.vhd
    Info (12022): Found design unit 1: Sample_NG-RTL
    Info (12023): Found entity 1: Sample_NG
Info (12021): Found 2 design units, including 0 entities, in source file sample.vhd
    Info (12022): Found design unit 1: Sample
    Info (12022): Found design unit 2: Sample-body
Info (12127): Elaborating entity "sample_ng" for the top level hierarchy
Warning (10873): Using initial value X (don't care) for net "O" at sample_ng.vhd(8)
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "O" is stuck at GND
    Warning (13410): Pin "O" is stuck at GND
    Warning (13410): Pin "O" is stuck at GND
    Warning (13410): Pin "O" is stuck at GND
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 2 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLK"
    Warning (15610): No output dependent on input pin "CLR"
Info (21057): Implemented 6 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 2 input pins
    Info (21059): Implemented 4 output pins
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 9 warnings
    Info: Peak virtual memory: 870 megabytes
    Info: Processing ended: Tue Mar 15 00:50:38 2016
    Info: Elapsed time: 00:00:25
    Info: Total CPU time (on all processors): 00:00:56