Wrong logic synthesis when call function named <package_name>.<function_name>

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???? http://www.alteraforum.com/forum/showthread.php?t=51340

ok. Did you pay attention on the word "all" in "use" clause?

by the way, why multiple call to "use" and "library" if VHDL able only one "use" clause per entity.

library ieee;

use ieee.std_logic_1164.all, ieee.numeric_std.all, work.sample.all;

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This doesnt matter. VHDL allows you to invidually call functions from a package. So this is not the problem. you never have to use .all to access things in a package, and you can also include only specific parts of packages if you want:

use ieee.std_logic_1164.std_logic; --cannot create std_logic_vectors

To the OP : this is very similar to your problem you posted here: http://www.alteraforum.com/forum/showthread.php?t=51340&p=211717#post211717

Have Altera confirmed the bug?