Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Wrong logic synthesis when call function named <package_name>.<function_name>

I am in trouble in VHDL analyze & synthesis. I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition". It defines the no argument function in the package. sample.vhd ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

At the end of the day, this appears to be a very convoluted solution to a very simple problem - is there any reason you are doing all of this with functions? if you step away from normal working practice, you are likely to hit tool bugs.