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Altera_Forum
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10 years ago

Wrong logic synthesis when call function named <package_name>.<function_name>

I am in trouble in VHDL analyze & synthesis. I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition". It defines the no argument function in the package. sample.vhd ...
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Altera_Forum
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10 years ago

Thank you for the reply.

The purpose of this thread is to provide, for sharing information, not that ask how to resolve.

http://www.alteraforum.com/forum/showthread.php?t=51340

As replied in the thread of the above, this problem has already been reported for Altera.

Altera is so plans of bug fixes in Quartus 16.1.