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Altera_Forum
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10 years ago

Wrong logic synthesis when call function named <package_name>.<function_name>

I am in trouble in VHDL analyze & synthesis. I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition". It defines the no argument function in the package. sample.vhd ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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Hi, KAWAZOME san,

Maybe, their replay had offended you, but they aren't kidding you. They only insist that 'If you have a workaround, don't enter the minefield'.

This forum is maintained by many volunteers. Of course, we have the person of Altera company, too. And all people are struggling to solve their problems with mutual cooperation.

Kazu

--- Quote End ---

Thank you for reply, Kazuyasu san.

But,,, I do not want to participate again this unpleasant forum.

Good bye.