Wrong logic synthesis when call function named <package_name>.<function_name>

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???? http://www.alteraforum.com/forum/showthread.php?t=51340

ok. Did you pay attention on the word "all" in "use" clause?

by the way, why multiple call to "use" and "library" if VHDL able only one "use" clause per entity.

library ieee;

use ieee.std_logic_1164.all, ieee.numeric_std.all, work.sample.all;

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I think that I am easy to understand that do not use "all" in "use" clause.

for example.

package A is 
  subtype Code_Type is std_loigc_vector(3 downto 0);
  function New_Code return Code_Type;
end A;
package B is
  subtype Code_Type is unsinged(3 downto 0);
  function New_Code return Code_Type;
end B;
use work.A;
use work.B;
   :
   :
  signal  code_a : A.Code_Type := A.New_Code;
  signal  code_b : B.Code_Type := B.New_Code;
   :
   :

The purpose of this thread is because I wanted to share information, not knowing the solution.

Though VHDL has such a description method, it presents a question in what only a tool of Altera does not accept.

Thank you for a reply.