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Altera_Forum
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10 years ago

Wrong logic synthesis when call function named <package_name>.<function_name>

I am in trouble in VHDL analyze & synthesis. I use "Quartus Prime Verion 15.1.0 Build 185 10/21/2015 SJ Lite Edition". It defines the no argument function in the package. sample.vhd ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

???? http://www.alteraforum.com/forum/showthread.php?t=51340

ok. Did you pay attention on the word "all" in "use" clause?

by the way, why multiple call to "use" and "library" if VHDL able only one "use" clause per entity.

library ieee;

use ieee.std_logic_1164.all, ieee.numeric_std.all, work.sample.all;