What is mean of rhis critical warning and how to handle it?

The error is pretty self-explanatory; you have fed your PLL from a pin that is not a dedicated clock pin that can be directly connected to the PLL, hence the jitter performance may be compromised.

The solution is to use a clock source that the PLL is happier with.

Cheers,

Dave

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The error is pretty self-explanatory; you have fed your PLL from a pin that is not a dedicated clock pin that can be directly connected to the PLL, hence the jitter performance may be compromised.

The solution is to use a clock source that the PLL is happier with.

Cheers,

Dave

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Thanks very much, Dave. But how to decide a pin which can make the PLL happier?

The problem is the evaluation board has some specific pins which connected with FPGA chip, are clock signals for FPGA. In my system, I need a main clock. But a PLL is not happy with this main clcok pin, how can I handle this problem?

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But how to decide a pin which can make the PLL happier?

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The device handbook described the PLL and clock resources.

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The problem is the evaluation board has some specific pins which connected with FPGA chip, are clock signals for FPGA. In my system, I need a main clock. But a PLL is not happy with this main clcok pin, how can I handle this problem?

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Which evaluation board? Most evaluation boards have a 50MHz oscillator routed to several CLKIN pins.

When dealing with an evaluation board, you sometimes have to make a judgement call, eg., if the clock frequency you are creating in the PLL is low enough, and you are using the PLL output only as a digital clock (not an ADC or DAC sampling clock), then you can probably ignore the error. At a minimum, if you do ignore the error, you should download the configuration file and test whether or not the clock jitter is a problem.

Cheers,

Dave

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The device handbook described the PLL and clock resources.

Which evaluation board? Most evaluation boards have a 50MHz oscillator routed to several CLKIN pins.

When dealing with an evaluation board, you sometimes have to make a judgement call, eg., if the clock frequency you are creating in the PLL is low enough, and you are using the PLL output only as a digital clock (not an ADC or DAC sampling clock), then you can probably ignore the error. At a minimum, if you do ignore the error, you should download the configuration file and test whether or not the clock jitter is a problem.

Cheers,

Dave

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Hi Dave, to be accurate, I think I should say this is a development board instead of education board although it is listed in Altera website (http://www.dallaslogic.com/prod_cmc1003.htm).

This board has a 25Mhz oscillator and it seems it only connects with 1 clkin pin. I just have another question, if the board has multiple clkin pins for FPGA chip, if I use two pins for FPGA to drive different modules, the phase of clocks come from these two pins should be exactly same, right?

Thanks.

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If you cannot change the source of the clock driving the PLL due to fixed pins, keep in mind that this is a warning, not an error. If you run "derive_clock_uncertainty" in TimeQuest and look at the uncertainty on the output clocks from the PLL, if you can live with this level of uncertainty, then you can ignore this warning.

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Thanks. I use the command "derive_clock_uncertainty" but I didn't know I should check uncertainty in TimeQuest. I just see there is no warning in TimeQuest.

The reason I care this is because I confront mismatch between simulation and onboard debugging. I doubt it may be caused by this critical warning. So I remove one pll in my design (totally I used three plls) which has this critical warning. Although now the results in onboard debugging match with simulation, there is another problem arise, that one of the left two plls has the same critical warning as before. This means although I remove one pll, but after new routing, another pll is routed to be unhappy with the clkin pin again.

Hi Dave, could you please help me this question "if the board has multiple clkin pins for FPGA chip, if I use two pins for FPGA to drive different modules, the phase of clocks come from these two pins should be exactly same, right?"

Thanks very much.

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Hi Dave, could you please help me this question "if the board has multiple clkin pins for FPGA chip, if I use two pins for FPGA to drive different modules, the phase of clocks come from these two pins should be exactly same, right?"

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It depends on the board layout. Here's some clocking examples;

1) Single clock routed to a global CLKIN pin on the FPGA.

This clock can route on a global clock network and reach all logic cells in the FPGA.

2) CLKIN pin to PLL

FPGA handbooks list which CLKIN pins can route to specific PLLs. For example, a PLL on the left-side of a large device might only be able to use a clock pin on the left-side of a large device.

3) A common clock to two CLKIN pins to two PLLs

When designing a board, you should first check that your CLKIN and PLLs can meet your design requirements. For example, if I want to use transceivers on both the left and right side of a device, and those transceivers will only accept clocks on the left and right sides of the device, then at the board level I would take a common clock, split it two-ways, and then route those two signals to two clock pins on the FPGA. The transceivers on the left would use the clock on the left, while those on the right would use the clock on the right. Since the external clock sources are in common, I can cross clock domains internal to the FPGA, without worrying that FIFOs will over-flow or under-flow, since the clocks are phase-locked to a common source. The clock phase might not be aligned perfectly, but that is ok, since you can use a FIFO to cross clock domains.

4) Two CLKIN pins with independent clock sources

The link you provided has no details on your board (the link to the user manual is not yet available).

What is it that you are trying to do?

Cheers,

Dave

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It depends on the board layout. Here's some clocking examples;

1) Single clock routed to a global CLKIN pin on the FPGA.

This clock can route on a global clock network and reach all logic cells in the FPGA.

2) CLKIN pin to PLL

FPGA handbooks list which CLKIN pins can route to specific PLLs. For example, a PLL on the left-side of a large device might only be able to use a clock pin on the left-side of a large device.

3) A common clock to two CLKIN pins to two PLLs

When designing a board, you should first check that your CLKIN and PLLs can meet your design requirements. For example, if I want to use transceivers on both the left and right side of a device, and those transceivers will only accept clocks on the left and right sides of the device, then at the board level I would take a common clock, split it two-ways, and then route those two signals to two clock pins on the FPGA. The transceivers on the left would use the clock on the left, while those on the right would use the clock on the right. Since the external clock sources are in common, I can cross clock domains internal to the FPGA, without worrying that FIFOs will over-flow or under-flow, since the clocks are phase-locked to a common source. The clock phase might not be aligned perfectly, but that is ok, since you can use a FIFO to cross clock domains.

4) Two CLKIN pins with independent clock sources

The link you provided has no details on your board (the link to the user manual is not yet available).

What is it that you are trying to do?

Cheers,

Dave

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Thanks so much for detailed answers, Dave. The problem I confront is it seems the development board only connects oscillator to one CLKIN pin. But now it reports the critical error when I want to use 3 plls in my chip. I think I should read the board manual carefully to see whether there are other clkin pins which connect to oscillator. Otherwise, it means this development board has big problem!

Thanks.

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The problem I confront is it seems the development board only connects oscillator to one CLKIN pin. But now it reports the critical error when I want to use 3 plls in my chip.

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You should look at the warning message and then review the handbook for the FPGA. Look at the PLLs that Quartus is trying to use, and then confirm that the CLKIN pin available cannot be used by one or more of your PLLs. That way you understand the synthesis error. You may not be able to do anything about the error, but you will know to avoid this problem when designing your own hardware.

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I think I should read the board manual carefully to see whether there are other clkin pins which connect to oscillator. Otherwise, it means this development board has big problem!

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The board is just a bunch of headers, you could always supply another clock source.

If the clock frequency is not that high, you could also drive a PLL output to a pin then jumper that pin over to another CLKIN input.

You can also cascade PLLs; use a PLL reference clock that is the output of another PLL on the FPGA. You may get warnings regarding jitter, but if you are just testing ideas, then that may not matter.

And finally, why do you need so many clocks?

Cheers,

Dave