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If you cannot change the source of the clock driving the PLL due to fixed pins, keep in mind that this is a warning, not an error. If you run "derive_clock_uncertainty" in TimeQuest and look at the uncertainty on the output clocks from the PLL, if you can live with this level of uncertainty, then you can ignore this warning.
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Thanks. I use the command "derive_clock_uncertainty" but I didn't know I should check uncertainty in TimeQuest. I just see there is no warning in TimeQuest.
The reason I care this is because I confront mismatch between simulation and onboard debugging. I doubt it may be caused by this critical warning. So I remove one pll in my design (totally I used three plls) which has this critical warning. Although now the results in onboard debugging match with simulation, there is another problem arise, that one of the left two plls has the same critical warning as before. This means although I remove one pll, but after new routing, another pll is routed to be unhappy with the clkin pin again.
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