What is mean of rhis critical warning and how to handle it?

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The error is pretty self-explanatory; you have fed your PLL from a pin that is not a dedicated clock pin that can be directly connected to the PLL, hence the jitter performance may be compromised.

The solution is to use a clock source that the PLL is happier with.

Cheers,

Dave

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Thanks very much, Dave. But how to decide a pin which can make the PLL happier?

The problem is the evaluation board has some specific pins which connected with FPGA chip, are clock signals for FPGA. In my system, I need a main clock. But a PLL is not happy with this main clcok pin, how can I handle this problem?