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But how to decide a pin which can make the PLL happier?
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The device handbook described the PLL and clock resources.
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The problem is the evaluation board has some specific pins which connected with FPGA chip, are clock signals for FPGA. In my system, I need a main clock. But a PLL is not happy with this main clcok pin, how can I handle this problem?
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Which evaluation board? Most evaluation boards have a 50MHz oscillator routed to several CLKIN pins.
When dealing with an evaluation board, you sometimes have to make a judgement call, eg., if the clock frequency you are creating in the PLL is low enough, and you are using the PLL output only as a digital clock (not an ADC or DAC sampling clock), then you can probably ignore the error. At a minimum, if you do ignore the error, you should download the configuration file and test whether or not the clock jitter is a problem.
Cheers,
Dave
Honored Contributor
