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The device handbook described the PLL and clock resources.
Which evaluation board? Most evaluation boards have a 50MHz oscillator routed to several CLKIN pins.
When dealing with an evaluation board, you sometimes have to make a judgement call, eg., if the clock frequency you are creating in the PLL is low enough, and you are using the PLL output only as a digital clock (not an ADC or DAC sampling clock), then you can probably ignore the error. At a minimum, if you do ignore the error, you should download the configuration file and test whether or not the clock jitter is a problem.
Cheers,
Dave
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Hi Dave, to be accurate, I think I should say this is a development board instead of education board although it is listed in Altera website (
http://www.dallaslogic.com/prod_cmc1003.htm).
This board has a 25Mhz oscillator and it seems it only connects with 1 clkin pin. I just have another question, if the board has multiple clkin pins for FPGA chip, if I use two pins for FPGA to drive different modules, the phase of clocks come from these two pins should be exactly same, right?
Thanks.
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