Verilog conditional compilation: `defines and `ifdefs

Are you explicitly adding your source files to the project or do you expect QII to find them automatically? In a compile, once QII sees a `define, it will be visible to all Verilog source files that are analyzed (parsed) later. This is actually a rather nasty behavior that's defined by the IEEE standard. In SystemVerilog, there's a concept of a compilation unit that can break the global scope of `defines. In fact, the SV standard says that each file should be a unique compilation unit by default...or at least, each file compiled separately on the command line. I believe Modelsim switched to this behavior even when compiling pure Verilog designs.

I add files to the project explicitly. But until I can reproduce the problem again I can't add much more. I guess a better solution would be to put all defines in a separate config.h.

Quartus II caches elaborated netlists in the database. When you hit Play again, it re-uses them unless something relevant (a source file, a macro, etc.) makes them stale. Years ago, the software sometimes re-used a netlist when it shouldn't, but I haven't personally experienced or heard about similar problems in recent memory. Maybe because people simply wipe the database when anything inexplicable happens and get on with life. Were you changing the `define after having run a compile?

Okay Josh, thanks for the hint! I'm aware of the old "wipe the db if everything fails" trick but it didn't work for me that time. Of course I was changing the defines after several compile runs and it was QII-WE-7.1. Will write back when/if it happens again. I have over a year of experience with Verilog and Quartus but anyway every time something like this (0 LE's in module, go figure, stuck clock?) happens I tend to panic.

I reproduced the situation. Same example as I described.. Top-level entity is defined as top in settings, but in the Project Navigator, top.v is second after foobar.v. In this case, a `define from top.v has no effect on foobar.v, even though top.v is a top-level entity. I couldn't see often before because I tend to put top-level file with all my defines at the top of list just for aesthetical reasons.

i hav used `define under if loops..but even if the condition fails, it seems that `define s executed.. can anyone help me..my prob in hand is that, i need to execute the same module with different parameters according to the input condition

Your situation is slightly unclear, but it seems that you expect a pre-processor directive to be guarded by a conditional generate statement. Pre-processor directives are resolved during the parsing of the design file, whereas conditional generates are resolved during elaboration. You should use conditional generates completely in place of pre-processor directives, if possible.

but for generate the condition need to be a constant expression and cannot the inputs. i want the parameter 'p' of a sub-module to change as the input 'i' changes.