Verilog conditional compilation: `defines and `ifdefs

I reproduced the situation. Same example as I described.. Top-level entity is defined as top in settings, but in the Project Navigator, top.v is second after foobar.v. In this case, a `define from top.v has no effect on foobar.v, even though top.v is a top-level entity. I couldn't see often before because I tend to put top-level file with all my defines at the top of list just for aesthetical reasons.