Verilog conditional compilation: `defines and `ifdefs

Okay Josh, thanks for the hint! I'm aware of the old "wipe the db if everything fails" trick but it didn't work for me that time. Of course I was changing the defines after several compile runs and it was QII-WE-7.1. Will write back when/if it happens again. I have over a year of experience with Verilog and Quartus but anyway every time something like this (0 LE's in module, go figure, stuck clock?) happens I tend to panic.