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Altera_Forum
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17 years ago

Verilog conditional compilation: `defines and `ifdefs

There was a helpful thread (http://www.alteraforum.com/forum/showthread.php?t=1996) about configuring `defines in .qsf file. I use conditional compilation to optionally remove parts of code from comp...
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Altera_Forum
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16 years ago

but for generate the condition need to be a constant expression and cannot the inputs. i want the parameter 'p' of a sub-module to change as the input 'i' changes.