Verilog conditional compilation: `defines and `ifdefs

Are you explicitly adding your source files to the project or do you expect QII to find them automatically? In a compile, once QII sees a `define, it will be visible to all Verilog source files that are analyzed (parsed) later. This is actually a rather nasty behavior that's defined by the IEEE standard. In SystemVerilog, there's a concept of a compilation unit that can break the global scope of `defines. In fact, the SV standard says that each file should be a unique compilation unit by default...or at least, each file compiled separately on the command line. I believe Modelsim switched to this behavior even when compiling pure Verilog designs.

Global defines are particularly troublesome for IP developers. A user can disable implicit net declarations with a compiler directive and thereby break the IP that relied on a perfectly legal (and totally insane) feature of the language.