Verilog conditional compilation: `defines and `ifdefs

Quartus II caches elaborated netlists in the database. When you hit Play again, it re-uses them unless something relevant (a source file, a macro, etc.) makes them stale. Years ago, the software sometimes re-used a netlist when it shouldn't, but I haven't personally experienced or heard about similar problems in recent memory. Maybe because people simply wipe the database when anything inexplicable happens and get on with life. Were you changing the `define after having run a compile?