Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Verilog conditional compilation: `defines and `ifdefs

There was a helpful thread (http://www.alteraforum.com/forum/showthread.php?t=1996) about configuring `defines in .qsf file. I use conditional compilation to optionally remove parts of code from comp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

i hav used `define under if loops..but even if the condition fails, it seems that `define s executed.. can anyone help me..my prob in hand is that, i need to execute the same module with different parameters according to the input condition