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Altera_Forum
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17 years ago

Verilog conditional compilation: `defines and `ifdefs

There was a helpful thread (http://www.alteraforum.com/forum/showthread.php?t=1996) about configuring `defines in .qsf file. I use conditional compilation to optionally remove parts of code from comp...
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Altera_Forum
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17 years ago

I add files to the project explicitly. But until I can reproduce the problem again I can't add much more. I guess a better solution would be to put all defines in a separate config.h.

`default_nettype none is my first line in every .v file I create. I suffered terribly before I discovered this fantastic feature ;)