TimeQuest ALTPLL wrong setup relation

yes, and exactly how does that anwser my question ?

also see 4.2.8.4. Normal Compensation Mode (intel.com) page 92...

Thanks,

Do you think for now relation can be 'fixed' by setting set_max_delay set_min_delay between those clocks ?

Hello,

I don't think so. Wouldn't it ignore the first phase shift that you have set?

Please refer to this documentation:

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/fpga-wiki/asset02/timequest-user-guide.pdf#page=59

Regards,

Nurina

Hi,

Engineering is still investigating the problem here.

I've tried experimenting by adding phase shift in the PLL.

With below SDC constraints,

create_clock -name {i_clk} -period 10.000 -waveform { 4.000 9.000 } [get_ports {i_clk}]

derive_pll_clocks

derive_clock_uncertainty

Added below changes to the PLL:

The setup & hold relationship is 10ns & 0ns respectively:

Setup Report Timing

Hold Report Timing

Can you try this solution?

Regards,

Nurina

Hello,

Have you tried the solution I have provided?

By the way, engineering has responded. Can you let me know why you are setting an offset to the base clock? What's the use case?

Regards,

Nurina

Hi,

so solution in principle works if I apply this values postpriori to pll settings - still there is question if actually router know what its doing in term of route path optimizations.

regarding the question about why clock offset is done - it was just simple example - in actual project clock edges are in 0 ns offeset -period 10.000 -waveform { 0.000 5.000 } [get_ports {i_CLK}] -> this clock describes incoming clk from ADC lvds interface that has 0 degrees clock to data edge offset. It is ALTLVDS_RX ipcore that produces phase shifted versions by x ns described above. For signal processing purpose as well as for resource sharing we need this clock exact copy that runs with same and 2 times faster frequency and thats when we find this abnormal behaviour if we connect ALTLVDS_RX ipcore output clock to ALTPLL ipcore.

Hello,

Thanks for the response.

I'm checking with engineering on the consequences of using this solution, I'll let you know of any updates.

Regards,

Nurina

Hello,

Engineering has provided a solution. I will attach the .sdc file.

Please use this .sdc file in place of derive_pll_clocks.

You may receive a warning "PLL cross checking found inconsistent PLL clock settings." which you can ignore.

For future references, what I've done is:

1. On Timing Analyzer, run derive_pll_clocks and then run write_sdc -expand myexpanded.sdc
2. On the create_generated_clock -name {*|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} add an offset so that the rising edge of this clock matches the rising edge of the base clock that feeds into the PLL.

Regards,

Nurina

I can't attach the .sdc file, but here's the sdc commands for -waveform {8.000 13.000}

##**************************************************************

## Create Clock

##**************************************************************

create_clock -name {i_clk} -period 10.000 -waveform { 8.000 13.000 } [get_ports {i_clk}]

#

##**************************************************************

## Create Generated Clock

##**************************************************************

#

create_generated_clock -name {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -offset 6.666 -multiply_by 6 -divide_by 2 -master_clock {i_clk} [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]

create_generated_clock -name {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]

#

##**************************************************************

## Set Clock Latency

##**************************************************************

#

#

#

##**************************************************************

## Set Clock Uncertainty

##**************************************************************

derive_clock_uncertainty

Can you also share the design you have used for Pro?

This is for the engineering team so they can refer to it.

I am seeing problems from my end somehow.

Regards,

Nurina