TimeQuest ALTPLL wrong setup relation

I can't attach the .sdc file, but here's the sdc commands for -waveform {8.000 13.000}

##**************************************************************

## Create Clock

##**************************************************************

create_clock -name {i_clk} -period 10.000 -waveform { 8.000 13.000 } [get_ports {i_clk}]

#

##**************************************************************

## Create Generated Clock

##**************************************************************

#

create_generated_clock -name {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} -source [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin}] -duty_cycle 50/1 -offset 6.666 -multiply_by 6 -divide_by 2 -master_clock {i_clk} [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]

create_generated_clock -name {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} -source [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]}] -duty_cycle 50/1 -multiply_by 1 -divide_by 3 -master_clock {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} [get_pins {project_pll|pll_in_normal_mode_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]

#

##**************************************************************

## Set Clock Latency

##**************************************************************

#

#

#

##**************************************************************

## Set Clock Uncertainty

##**************************************************************

derive_clock_uncertainty