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toczkows
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3 years ago

TimeQuest ALTPLL wrong setup relation

Hi, recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
toczkows's avatar
toczkows
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3 years ago

Thanks,

Do you think for now relation can be 'fixed' by setting set_max_delay set_min_delay between those clocks ?