Forum Discussion
toczkows
New Contributor
3 years agoTimeQuest ALTPLL wrong setup relation
Hi,
recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
Nurina
Regular Contributor
3 years agoHello,
Thanks for the response.
I'm checking with engineering on the consequences of using this solution, I'll let you know of any updates.
Regards,
Nurina