TimeQuest ALTPLL wrong setup relation

Hello,

Engineering has provided a solution. I will attach the .sdc file.

Please use this .sdc file in place of derive_pll_clocks.

You may receive a warning "PLL cross checking found inconsistent PLL clock settings." which you can ignore.

For future references, what I've done is:

1. On Timing Analyzer, run derive_pll_clocks and then run write_sdc -expand myexpanded.sdc
2. On the create_generated_clock -name {*|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} add an offset so that the rising edge of this clock matches the rising edge of the base clock that feeds into the PLL.

Regards,

Nurina