Forum Discussion
toczkows
New Contributor
3 years agoTimeQuest ALTPLL wrong setup relation
Hi,
recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
Nurina
Regular Contributor
3 years agoCan you also share the design you have used for Pro?
This is for the engineering team so they can refer to it.
I am seeing problems from my end somehow.
Regards,
Nurina