Forum Discussion

toczkows's avatar
toczkows
Icon for New Contributor rankNew Contributor
3 years ago

TimeQuest ALTPLL wrong setup relation

Hi, recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

Engineering is still investigating the problem here.

I've tried experimenting by adding phase shift in the PLL.

With below SDC constraints,

create_clock -name {i_clk} -period 10.000 -waveform { 4.000 9.000 } [get_ports {i_clk}]

derive_pll_clocks

derive_clock_uncertainty

Added below changes to the PLL:

The setup & hold relationship is 10ns & 0ns respectively:

Setup Report Timing

Hold Report Timing

Can you try this solution?

Regards,

Nurina