New Contributor
New ContributorHi,
so solution in principle works if I apply this values postpriori to pll settings - still there is question if actually router know what its doing in term of route path optimizations.
regarding the question about why clock offset is done - it was just simple example - in actual project clock edges are in 0 ns offeset -period 10.000 -waveform { 0.000 5.000 } [get_ports {i_CLK}] -> this clock describes incoming clk from ADC lvds interface that has 0 degrees clock to data edge offset. It is ALTLVDS_RX ipcore that produces phase shifted versions by x ns described above. For signal processing purpose as well as for resource sharing we need this clock exact copy that runs with same and 2 times faster frequency and thats when we find this abnormal behaviour if we connect ALTLVDS_RX ipcore output clock to ALTPLL ipcore.
