New ContributorTimeQuest ALTPLL wrong setup relation
Hi,
recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output of PLL (sys_clk) (1:1 ratio "normal" mode) from same clock, then for STA setup and hold time relationshiops are dependant on waveform (phase shift) from main clock (i_CLK) that I create.
So for example in sdc:
create_clock -name {i_CLK} -period 10.000 -waveform { 0.000 5.000 } [get_ports {i_CLK}]
derive_pll_clocks
derive_clock_uncertainty
setup is 10 ns and hold is 0 ns as expected
but for constraints
create_clock -name {i_CLK} -period 10.000 -waveform { 8.000 13.000 } [get_ports {i_CLK}]
derive_pll_clocks
derive_clock_uncertainty
setup is 3.334 ns and hold -6.636 ns
From the clock tree perspective it looks like STA takes clock edges and apply it to nearest PLL VCO edge and apply that as output waveform phase shift and this leads to unrealistic timing (?) requirements that are dependand on arbitrary waveform generation in sdc, where it shouldn't be a case.
How to handle this situation - override setup/hold with set_max/min_delay ?
Moreover in Quartus Prime Pro everythink works as exptected and relation stays always the same - ts 10.0 th 0.00
Regards
