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toczkows's avatar
toczkows
Icon for New Contributor rankNew Contributor
3 years ago

TimeQuest ALTPLL wrong setup relation

Hi, recently I found some strange behaviour of timequest STA regarding simple design with PLL on Quartus Prime Lite. If there is simple data transfer between clock (i_CLK) and clock that's output ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello,


As mentioned above, when you create a phase shift this will affect the setup and hold relationships.

Can you share the .qar file of your design? From there I might be able to understand your question better.


Regards,

Nurina


  • toczkows's avatar
    toczkows
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi

    I'll prepare .qar tomorrow.